FET Silicon Nanowires (SiNW) have emerged as promising candidates for a new generation of label-free real-time sensors [1] for the detection of chemical and biological species. Even though SiNWs' potential for sensing has been largely proven and the knowledge of sensing mechanisms widely extended, mass-production and integration of such sensors has still to face many challenges. This patent proposes an alternative sensor, able to provide better performance, especially in terms of stability and reliability. It also guarantees a direct integration with CMOS read-out electronics, preserving its performances upon scaling.
FinFET as State-of-the-Art Transistor:
The first fabricated non-planar FET was proposed in 1989 as “fully DEpleted Lean-channel TrAnsistor (DELTA)” by Hisamoto et al. [2], as illustrated in FIG. 1.A. The term FinFET was actually referring to the same DELTA structure but with an additional top hard-mask [3] used to avoid parasitic inversion at the corners, as shown in FIG. 1.B. Commonly today and in this document, the term FinFET is used for both architectures. The DELTA and the FinFET are part of a group of transistors which can generally be referred to as multi-gate FETs (MG-FET) including double-gate (DG), triple and surrounding gate transistors [4]. These architectures have been developed to overcome the adverse effects that come along with CMOS scaling for higher switching speed and more densely integrated circuits according to Moore's law [5].
Some of the mentioned non-ideal effects have been identified as: (i) short-channel effects including voltage roll-off, (ii) drain-induced barrier lowering (DIBL), (iii) subthreshold slope degradation and (iv) non-negligible parasitic components [6]. Using a multi-gate architecture, a better control of the channel depletion is obtained with respect to a standard MOSFET and the influence of the drain electric field on the channel is reduced. Looking towards sensor CMOS integration, the scaling compatibility is an indispensable feature. Moreover, the advanced channel control provided by the FinFET architecture results in excellent sensor properties, as reported hereafter.
ISFET Principle:
Ion Sensitive Field Effect Transistors (ISFET) were first developed in the 1970s, as an alternative to the glass electrodes for pH and ion measurements. In comparison with a MOSFET (FIG. 2.A), the gate electrode is replaced by a reference electrode immersed in an aqueous solution in contact with the gate oxide, as illustrated in FIG. 2.B.
The voltage at the silicon surface is then function of the reference electrode and the amount of charges present in the solution as long as their contribution is not negligible at the ISFET surface. With respect to the voltage gate Vg of standard MOSFET, additional contributions should then be considered [7]:
                              V          g                =                              E            ref                    -          Ψ          +                      χ            sol                    -                                    Φ              Si                        q                    -                                    Q              D                                      C              ox                                +                      ϕ            S                                              Eq        .                                  ⁢        1            
Where Eref is the potential of the reference electrode, Ψ is the chemical potential at the solution-oxide interface, χsol is the surface dipole potential of the solvent (usually constant), ΦSi is the work function of the silicon which has been separated from the usual ΦM of the metal gate now included in Eref and φS is the surface potential at the Si-Oxide interface which determines the Id(Vg) transfer characteristics.
Ψ and φS are both surface potentials but they refer to two different interfaces in series. Any chemical variation of the solution modifies Ψ, which in case of pH can be expressed as Ψ(pH), but it can depend on any other electrical charges related to other ions or biological entities (DNA, proteins). The contribution of Ψ is then linearly added to φS, meaning that the electronic properties of the FET expressed by the Id (Vref)) are not modulated by Ψ but only shifted by a ΔΨ. A change in Ψ will result in a change in the ISFET threshold voltage Vth, which can be measured by sweeping the reference electrode or by monitoring the Id value at fixed Vref value.
Previous Works Related to SiNWs for Sensing Applications
A list of references related to SiNWs for sensing applications is here reported. Information on the technology implemented in each work is mentioned as follows:
Technology Approach:                Top-Down (TD): it consists in removing material from an initial substrate (e.g. silicon wafer) until structures are created;        Bottom-Up (BU): small items (e.g. atoms or molecules) are assembled to create a larger device.        
Silicon Substrate:                Bulk: single-crystal piece cut and polished from larger single-crystal ingots;        SOI: it consists of two silicon pieces separated by an insulator layer (usually SiO2).        
Architecture:                FinFET: HFin/TFin at least >1;        Ribbon FET: WRibbon/TRibbon>1, including trapezoidal and triangular shape where Wbottom>TRibbon;        ISFET: standard bulk MOSFET;        Trigate FET with: WFin/TFin≈1;        GAA: Gate-All-Around, circular wire.        
References Related to SiNWs for Sensing Applications:                This invention: TD, Bulk, FinFET        Microsens SA [8] TD, Bulk, ISFET                    Based on a standard MOSFET structure                        Abe et al. [9] TD, Bulk, ISFET                    Based on a standard MOSFET structure                        Lee et al. [10] TD, SOI, Ribbon FET        Park et al. [11] TD, SOI, Ribbon FET        Yoo et al. [12] TD, SOI, Ribbon FET        Kim et al. [13] TD, SOI, Trigate FET        Ahn et el. [14] TD, SOI, Trigate FET        Ahn et el. [15] TD, Bulk, top side of a vertical FET                    see comment below                        Vu et al. [16] TD, SOI, Ribbon FET        Cui et al. [17] TD, SOL GAA        Tarasov et al. [18] TD, SOI, Ribbon FET        Chen et al. [19] TD, SOI, Ribbon FET        Zhang et al. [20] TD, SOI, Trigate FET        Li et al. [21] TD, SOI, Trigate FET        Hahm et al. [22] BU, SOI, GAA        Stern et al. [23] TD, SOI, Ribbon FET        Zheng et al. [24] TD, SOI,        Kim et al. [25] TD, SOI, Ribbon FET        Li et al. [26] BU, SOI, GAA        Wang et al. [27] BU, SOI, GAA        Zhang et al. [28] TD, SOI, Ribbon FET        Chiang et al. [29] TD, SOI, Ribbon FET        Patolsky et al. [30] BU, SOI, GAA        
Most of the available references are based on Ribbon-like structures. Some are based on GAA SiNWs fabricated by a bottom-up approach, which are not CMOS compatible. In [15] the exploited sensing surface is only the top side of the vertical FET while the body is embedded and controlled by lateral gates which are used for amplification purposes. Only one planar side of the device is involved in the detection mechanism limiting the potential advantages of a multi-gate vertical architecture. Contrarily in this invention, as presented in the following sections, the double-gate structure is fully immersed in the solution and the channel potential is controlled exclusively by the surrounding environment.